Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to an electrically programmable, non-volatile memory cell configuration having a semiconductor substrate of a first conductivity type,
in which at least one first address line and at least one second address line are provided and the second address line crosses the first address line with a space between them; PA1 in which a memory cell is located essentially between the first address line and the second address line, is arranged at least partially in the semiconductor substrate and has, there, at least one first doped region of the second conductivity type forming a direct junction between the two conductivity types, in which case this junction allows an electrical current flow between the first address line and the second address line in the semiconductor substrate to be limited unidirectionally; and PA1 in which at least one intermediate layer, which is part of the memory cell, is located on the semiconductor substrate between the first address line and the second address line. PA1 a trench with at least one side wall is formed in the semiconductor substrate; PA1 at least one first address line running along the side wall of the trench in the substrate, and at least one second address line in the substrate crossing the first address line at a spaced distance therefrom; PA1 a memory cell substantially between the first address line and the second address line at least partially in the semiconductor substrate, the memory cell having at least one first doped region of a second conductivity type forming a direct junction between the first and second conductivity types, the direct junction allowing an electrical current flow between the first address line and the second address line in the semiconductor substrate to be limited unidirectionally; and PA1 at least one intermediate layer on the semiconductor substrate between the first address line and the second address line forming a part of the memory cell. PA1 the trench is one of a large number of trenches formed in the semiconductor substrate substantially parallel to one another and having webs disposed in between, the trenches have side walls on the webs and at least one first address line runs on each the side wall along the trenches; PA1 the webs have isolation regions extending transversely to the trenches, the isolation regions divide the webs into individual, mutually isolated, semiconductor substrate regions of the first conductivity type, whereby at least two first doped regions are located in each the semiconductor substrate region and are each associated with a respective memory cell; and each the semiconductor substrate region is connected to a respective the second address line running transversely to the first address lines and at a distance therefrom. PA1 providing a semiconductor substrate of a first conductivity type; PA1 forming mutually parallel isolation trenches in the semiconductor substrate; PA1 filling the isolation trenches with an insulating material and forming isolation regions in the isolation trenches; PA1 incorporating mutually parallel trenches transversely to the isolation trenches in the semiconductor substrate, retaining webs between the trenches, whereby the webs are subdivided by the isolation regions of the isolation trenches into individual semiconductor substrate regions of the first conductivity type; PA1 forming an intermediate layer on the side walls of the trenches; PA1 applying first address lines of a second conductivity type to the side walls of the trenches, whereby the first address lines contain a dopant of the second conductivity type; and PA1 heat-treating the semiconductor substrate at a predetermined diffusion temperature, and partially diffusing the dopant out of the first address lines, through the intermediate layer, and into the semiconductor substrate regions, for forming therein first doped regions of the second conductivity type with a direct junction to the first conductivity type.
The invention further pertains to a method of producing such a memory cell configuration.
A large number of different memories are used for data processing. For example, a computer contains both a read only memory ROM as well as a dynamic memory (Dynamic Random Access Memory) DRAM. DRAMs are so-called volatile memories, in which the stored information must be refreshed regularly. In contrast to this, data refreshing is not necessary in so-called read only memories (ROMs), since the data are stored permanently. Normally, data are stored in a read only memory during its production process. However, in contrast, programmable read only memories are more advantageous, in the case of which a suitable programming technique is used to write the information to these read only memories only after they have been produced. Such read only memories are also referred to as Programmable Read Only Memories (PROMs).
A programmable read only memory is described, for example, in U.S. Pat. No. 5,536,968 to Crafts et al. The essence of that read only memory is a diode matrix in which each matrix element comprises a diode and a thermal resistance element, and is connected to in each case one data input line and one data output line. The resistance elements, which are of relatively complex design, occupy a large amount of space and produce the connection between the data input lines and data output lines via the diodes, can be caused to melt by a current surge. This results in the electrical connection within a matrix element being interrupted, and thus in information being stored there. When the resistance element is intact, the matrix element represents, for example, a logic 1, while, in contrast, when the resistance element has been melted, it represents a logic 0. This information can subsequently be interrogated by checking the individual matrix elements.
A memory cell of the type mentioned initially is disclosed, for example, in U.S. Pat. No. 4,677,742 to Johnson. In that memory cell configuration, first address lines and second address lines which each run parallel to one another are arranged on a semiconductor substrate. The first address lines and second address lines cross, with a space between them formed by the semiconductor substrate. A so-called PIN diode has in each case been formed, by successive deposition of a plurality of semiconductor layers, at the intersections between the first address lines and second address lines. Furthermore, a layer whose resistance value can be changed once is located between each diode and each address line, whose resistance value governs the memory content of each individual memory cell located in the intersection area of the address lines. The space requirement for this memory cell configuration is, disadvantageously, relatively high. If, for example, the smallest technologically achievable structure width is denoted by F, then a memory cell in the memory cell configuration described by Johnson requires an area of 4 F.sup.2.